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0804-5000-25 industrial powerline module bel modules 28 turkey court, turkey mill, ashford road maidstone bel me 14 5pp uk +44 1622 757 395 techhelp@belf.com belfuse.com ? 2017 bel power solutions, inc. 1 the bel 0804-5000-25 single in line package (sip) m odule is an industrial temperature rated mac/phy/afe powerline communicati ons (plc) transceiver. the module complements the existing range of bel po werline modules based on the qualcomm atheros ar6400/ar1400 and is optimi zed for communications over coax networks. the bel 0804-5000-25 module enables the development of hd grade communications bridges to and from the coax network . it also serves as a translator between the digital and analogue world s. on the digital side host interfaces include ethernet mii host or phy. the data received and transmitted is translated by the ar6400 to and from a complex analogue signal which is modulated on multiple carriers and transmitted over the coax network. key features & benefits ? based on qualcomm atheros ar6400/ar1400 chipset ? based on homeplug? av standard optimized for ethern et over coax (eoc) applications with raw data rates up to 200 mb /s ? temperature rated for industrial applications ? mii (host & phy interface ? supports 1024/256/64/16/8-qam, qpsk, bpsk and robo modulation schemes ? 128-bit aes link encryption with key management for secure power line communications ? advanced turbo code forward error correction ? tos, cos and ip port number packet classifiers ? supports igmp managed multicast sessions ? green standard (rohs) compliant ? horizontal mounting configuration using standard 1. 27mm pin header ? integrates all components necessary to add ethernet over coax functionality to any embedded system at low cost applications ? over-the-top video ? telco/iptv ? ethernet-over-coax (eoc) and multi-dwelling unit (m du) applications
0804-5000-25 industrial powerline module techhelp@belf.com belpowersolutions.com 2 module block diagram module interface pin i/o table pin number pin name pin number pin name 1 vdd 26 mdc 2 vss 27 reserved (n.c.) 3 vdd 28 reserved (required connection to ground) 4 vss 29 vss 5 vdd 30 mrx_d0 6 tx+ 31 mrx_d1 7 tx- 32 mrx_d2 8 vss 33 mrx_d3 9 rx+ 34 col 10 rx- 35 mrx_clk 11 reset/ 36 vss 12 gpio0 37 mrx_err 13 gpio1 38 mrx_dv 14 gpio2 39 mtx_d0 15 gpio3 40 mtx_d1 16 gpio4 41 mtx_d2 17 gpio5 42 mtx_d3 18 gpio6 43 crs 19 gpio7 44 mtx_clk 20 gpio8 45 mtx_en 21 gpio9 46 vss 22 gpio10 47 phy_rst/ 23 gpio11 48 vss 24 reserved (required 10k pull up resistor) 49 phy_clk 25 mdio 50 vss
0804-5000-25 industrial powerline module techhelp@belf.com belpowersolutions.com 3 system block diagram this block diagram present the 0804-5000-25 powerli ne module in a typical environment. seven differen t types of interfaces are shown. these interfaces are described in detai l below. media independent interface (mii) the mii interface is configured as either an ethern et medium access controller (mac) or a physical med ium dependent (pmd or phy) controller. medium independent interface (mii ) is an industry standard, multi-vendor interface b etween the mac and phy sub-layers. it provides a simple connection betwee n ethernet phy controllers and ieee802.3 ethernet m acs from a variety of sources. mii consists of separate 4-bit data paths for trans mit and receive data along with carrier sense and c ollision detection. further details of the mii are available from the ieee 802. 3u standard. configuration straps described in section 3 set the mii operation to a mac or phy controller. the mac and phy configurations support 10 mbps or 100 mbps in half-duplex or full- duplex modes and flow control for half-duplex and f ull-duplex connections. the ethernet mac module implements standard etherne t mac functionality. the ethernet mac is connected to an external ethernet phy function. the mac configuration provi des bridging between ethernet and the powerline. t he phy configuration emulates ethernet phy functionality and provides ho meplug av connectivity to devices designed to commu nicate over an ethernet network. the mii (ethernet) interface has separate transmit and receive packet buffering. when operating as a mac the mii transmit fifo is 2 kb and the receive fifo is 8 kb. when operatin g as a phy controller, the mii transmit fifo is 8 k b and the receive fifo is 2 kb.
0804-5000-25 industrial powerline module techhelp@belf.com belpowersolutions.com 4 mii mac the mii mac configuration operates as an ieee 802.3 10/100-mbps ethernet mac connected to an external 10/100-mbps ethernet phy. when the power line module boots it attempts to con figure the mii mac interface, it will first scan al l external mii phys starting from phy #0 and will select the first phy that resp onds with valid register contents. the phys link status register will be read, and if the link is up, auto-negotiation will be performed . if the phys status indicates that auto-negotiation is not supported, auto-negoti ation will not be performed. based upon the results of the phys status register s, or auto-negotiation results, the phy will be con figured in an operational mode (i.e. no loopback, no collision test, not in i solate, etc.). the mii mac within the power line m odule will be configured for the same speed and duplex. external devices do not have direct access to any mii mac registers in the ar6400. mii phy the mii phy emulation hardware connects to an exter nal 10/100-mbps ethernet mac. the default phy func tionality is configured through standard management data interfa ce communications (mdi interface) and may be overri dden by the ar6400 mac firmware access to the phy emulation reg isters. the interface supports the standard control and status register. ? link speed at 10 mbps or 100 mbps ? full-duplex or half-duplex operation ? management date interface base address ? isolate to disconnect the phy from the mii port in mii phy mode, auto-negotiation is not supported. gpio strapping on the power line module will deter mine the desired configuration, these straps will be reflected in th e default settings in the mii phy emulation registe rs.
0804-5000-25 industrial powerline module techhelp@belf.com belpowersolutions.com 5 mii signals pin number pin name i/o description mac mode phy mode 30 31 32 33 mrx-d0 mrx-d1 mrx-d2 mrx - d3 i o mii receive data. the phy controller drives mrx_d[ 3:0] and the mac core receives mrx_d[3:0]. mrx_d[3:0] transition synchronously wi th respect to mrx_clk. for each mrx_clk period in which mrx_dv is asserted, mrx_d[3 :0] is valid. mrx_d0 is the least - significant bit. the phy controller tri - states mrx_d[3:0] in isolate mode. 34 col i o mii collision detected. the phy controller asserts col when it detects a collision on the medium. col remains asserted while the collision c ondition persists. col signal transitions are not synchronous to either the mtx_c lk or the mrx_clk. the mac core ignores the col signal when operating in the full-d uplex mode. the phy controller tristates col in isolate mode. 35 mrx_clk i o mii receive clock. mrx_clk is a continuous clock th at provides the timing reference for the transfer of the mrx_dv and mrx_d[3:0] signa ls from the phy controller to the mac core. the phy controller sources mrx_clk. mrx_ clk frequency is equal to 25% of the data rate of the received signal on the ethe rnet cable. the phy controller tri- states mrx_clk in isolate mode. 37 mrx_err i o mii receive error. the phy controller asserts mrx_ err high for one or more mrx_ clk periods to indicate to the mac core that an error ( a coding error or any error that the phy is capable of detecting that is otherwise undet ectable by the mac) was detected somewhere in the current frame. mrx_err transition s synchronously with respect to mrx_clk. while mrx_dv is de-asserted, mrx_err has n o effect on the mac core. the phy controller tri-states mrx_err in isolate mode. 38 mrx_dv i o mii receive data valid. the phy controller asserts mrx_dv to indicate to the mac core that it is presenting the recovered and decoded dat a bits on mrx_d[3:0] and that the data on mrx_d[3:0] is synchronous to mrx_clk. mrx_ dv transitions synchronously with respect to mrx_clk. mrx_dv remains asserted c ontinuously from the first recovered nibble of the frame through the final rec overed nibble, and is de-asserted prior to the first mrx_clk that follows the final n ibble. the phy controller tri-states mrx_dv in isolate mode. 39 mtx_d0 o i mii transmit data. the mac core drives mtx_d[3:0] and the phy controller receives mtx_d[3:0]. mtx_d[3:0] transitions synchronously w ith respect to mtx_clk. for each mtx_clk period in which mtx_en is asserted, mt x_d[3:0] is valid. mtx_d0 is the least significant bit. the phy controller igno res mtx_d[3:0] in isolate mode. 40 mtx_d1 41 mtx_d2 42 mtx_d3 43 crs i o mii carrier sense. the phy controller asserts crs when either transmit or receive medium is non-idle. the phy de-asserts crs when bo th transmit and receive medium are idle. the phy must ensure that crs remains ass erted throughout the duration of a collision condition. the transitions on the crs si gnal are not synchronous to either the mtx_clk or the mrx_clk. the phy controller tri-sta tes crs in isolate mode. 44 mtx_clk i o mii transmit clock. mtx_clk is a continuous clock t hat provides a timing reference for the transfer of the mtx_en and mtx_d[3:0] signals f rom the mac core to the phy controller. the phy controller sources mtx_clk. t he operating frequency of mtx_clk is 25 mhz when operating at 100 mbps and 2.5 mhz wh en operating at 10 mbps. the phy controller tri - states mtx_clk in isolate mode. 45 mtx_en o i mii transmit enable. a high assertion on mtx_en in dicates that the mac core is presenting nibbles to the phy controller for transm ission. the ar6400 mac core asserts mtx_en with the first nibble of the preambl e and keeps mtx_en asserted while all nibbles to be transmitted are presented t o the mii .mtx_en is de-asserted prior to the first mtx_clk following the final nibb le of the frame. mtx_en transitions synchronously with respect to mtx_clk. the phy cont roller ignores mtx_en in isolate mode. special care must be taken during pcb layout of the mii bus. keep mii signal traces as short as possi ble and preferably on inner pcb layers.
0804-5000-25 industrial powerline module techhelp@belf.com belpowersolutions.com 6 mii management data interface (mdi) the mii interface has a two-wire bi-directional ser ial management data interface (mdi). this interfac e provides access to the status and control registers in the ethernet phy logic. t he mii and mdi pins are shared between the mac and phy interfaces. pin number pin name i/o description mac mode phy mode 25 mdio i/o i/o mii management data in/out. this is the data input signal from the phy controller. the phy drives the read data synchr onously with respect to the mdc clock during the read cycles. t his is also the data output signal from the mac core that drives the con trol information during the read/write cycles to the phy controller. the mac core drives the mdo signal synchronously with respect to the mdc. an external pull - up resistor is needed on this pin. 26 mdc o i/o mii management data clock. the mac core sources md c as the timing reference for transfer of information on the mdio signal. mdc signal has no maximum high or low times. mdc mi nimum high and low times are 160 ns each, and the minimum peri od for mdc is 400 ns. general purpose input/output (gpio) pins interface general purpose i/o pins are software programmable inputs or outputs, which can also be used as an ext ernal interrupt source. as indicated in the table below, some of these gpio signals also have additional functionality as conf iguration straps. see section 3 for configuration options. pin number pin name configuration strap function i/o internal pull up/down 12 gpio0 n/a s.c up 13 gpio1 n/a s.c up 14 gpio2 n/a s.c up 15 gpio3 isodef s.c up 16 gpio4 speed s.c up 17 gpio5 md_a3 s.c up 18 gpio6 cfg_sel s.c down 19 gpio7 md_a4 s.c down 20 gpio8 mp_sel s.c up 21 gpio9 n/a s.c down 22 gpio10 bm_sel s.c down 23 gpio11 n/a s.c down *s.c. = software configurable
0804-5000-25 industrial powerline module techhelp@belf.com belpowersolutions.com 7 in addition to their configuration strap function, the gpios can perform some software configurable fu nctions after reset. the default configuration provided by bel fuse is as be low: gpio i/o default function after reset gpio0 o not used (hiz) gpio1 i typically connected to a push-button. this gpio is used to add a new device to, or remove an old devic e from, a homeplug ac logical network. contact bel fuse for f urther information. gpio2 i typically connected to a push-button. the factory d efault can be restored by applying a low-level digi tal voltage on gpio2 for greater than 0.5 seconds and less than 3.0 seconds. gpio [3..7] o not used (hiz) gpio8 o to be connected to an led. the led gives indication s about powerline link & activity. on: powerline link detected. flash: tx or rx powerline activity (error! referenc e source not found). off: powerline link not detected. gpio9 o to be connected to an led. the led gives indication s about ethernet link & activity. on: ethernet link detected. flash: transmit or receive activity. off: no link detected. gpio10 o to be connected to an led. the led gives indication s about powerline mode. on: homeplug1.0trafficdetected. flash: n/a off: silence. gpio11 o to be connected to an led. the led gives indication about power. on: power ready. flash: load firmware. (error! reference source not found). off: power not ready. 1. the power line link led indicator turns on when powerline link is detected. if the ar6400 module is serving as a station (sta), the led indicator will flash to indicate transmit o r receive powerline activity. if the int6400 modul e is serving as a cco (central coordinator), the led indicator will light steadily on, even in the presence of powerline activity. 2. if module flash memory is corrupted/blank or a host processor does not provide fw, the module rom based code will blink the power led on and off at a frequency of one cycle pe r second. phy utility interface pin number pin name i/o description 47 phy_rst/ o phy device reset (active low). connect to an exter nal ethernet phy. this reset output is a stretched version of the reset/ input. 49 phy_clk o 25mhz clock out. this output is a dedicated clock output that can be used to drive the clock input on an external ethernet phy. this clock output is only available when the ar6400 is configured in mac mode, and not in ph y mode of operation. note that if this output is used, it is strongly advised that the corresponding phy_rst/ signal also be connected to the external ethernet p hy. coupling interface pin number pin name i/o description 6 tx+ o differential tx line driver output, connects to cou pling 7 tx- o differential tx line driver output, connects to cou pling 9 rx+ i differential rx line filter input, connects to coup ling 10 rx- i differential rx line filter input, connects to coup ling
0804-5000-25 industrial powerline module techhelp@belf.com belpowersolutions.com 8 special care must be taken during pcb layout of the coupling interface signals. route differential pa irs close together and away from all other signals. route each differential pair on the same pcb layer. keep both traces of each diff erential pair as identical to each other as possible. wide copper is needed here to support current densi ty of up to 30mhz. these high frequencies result i n higher resistance due to skin effect. the wide traces also accommodate high transient currents caused by voltage spikes. trac e widths between the module and the coupling transformer must be no less than 0 .020 (0.5 mm) and should be no greater than 0.030 (0.75 mm). reset interface pin number pin name i/o description 11 reset/ i resets all ic logic when low. power interface pin number pin name i/o description 1,3,5 vdd i +3.3v with respect to vss 2, 4, 8, 29, 36, 46, 48, 50 vss i ground reserved pins internally connected and reserved for future use. pin number type description 24 reserved required 10k pull-up resistor 27 reserved do not connect externally 28 reserved required connection to ground configuration options the ar6400 mii and boot options are selected by the initial condition of gpio pins. if a gpio pin is not used and its internal strapping resistor sets the booting option correctl y, then the pin may be left unconnected. if a gpio pin is not used but the internal strapping resistor sets the booting option incorrectly, then the pin must be pulled high or l ow to the correct booting option by an external resistor. this resistor can b e 10 k-ohms down to a few hundred ohms. 3.3 k-ohms is typical. many gpio pins are driven by firmware for led output immediat ely after boot up so connecting these gpio directly to ground or vdd is unacceptable. pin number pin name strap function internal pull up/down default function 15 gpio3 isodef up phy mode: hi-z mii interface 16 gpio4 speed up phy mode: 100mbps 17 gpio5 md_a3 up phy mode: phy address 0x0100 18 gpio6 cfg_sel down boot: sdram parameters from host 19 gpio7 md_a4 down phy mode: phy address 0x0100 20 gpio8 mp_sel up host: mac mode 22 gpio10 bm_sel down boot: firmware from host 49 phy_clk duplex up phy mode: full duplex
0804-5000-25 industrial powerline module techhelp@belf.com belpowersolutions.com 9 mii options the mp_sel strap is used to specify whether the ar6 400 chip is configured for mii mac mode, or in mii phy mode (i.e. reverse- mii mode). the encoding of this signal is shown in the following table: mp_sel mode 0 mii in phy mode 1 mii in mac mode mii phy mode, there are 4 additional configuration straps that are unique to this mode of operation: speed mii speed duplex mii duplex 0 10mbps 0 half duplex 1 100mbps 1 full duplex isodef isolation md_a[3,4] mii management address 0 normal operation 00 0x00 1 isolated 01 0x08 10 0x10 11 0x18 boot options the bm_sel strap is used to determine the source of the boot code for the embedded arm processor. sim ilarly, the cfg_ sel strap is used to determine the source of the sdram config uration applet. the encodings for these two signal s is shown in the following table. bm_sel cfg_sel meaning 0 0 load sdram configuration and boot code from externa l host 0 1 load sdram configuration applet from flash, and the n load boot code from external host 1 0 not supported 1 1 load sdram configuration and boot code from flash design notes leave below lines unconnected if they are not unuse d: ? pin 47: phy_rst# ? pin 49: phy_clk ? pin 27: reserved ? connect pin 28 (reserved) signal to the ground. ? zero-cross detection circuit is not required for dc line connection, but to work correctly the plc mod ule requires a pull- up resistor (10k) on zc_in line ? do not force other logic levels than default during the module boot on reserved gpio strappings, gpio 0-2 and 3. ? when the powerline module is in phy mode, rx_er sig nal should not be connected to the mii bus. this li ne is not tri- stated. use a 10k ohm pull down resistor only.
0804-5000-25 industrial powerline module techhelp@belf.com belpowersolutions.com 10 firmware the 0804-5000-25 powerline modules are supplied pro grammed with the most recent firmware versions and default parameter information block (pib) for eoc from qualcomm ather os. the pib contains the parameters used to config ure the operation of the ar6400 chipset, including: ? network management key (nmk), ? mac address ? device access key (dak), ? gpio function after reset. this factory default pib can be superseded by a cus tomized user pib using the avitar pc-based applicat ion. a non-disclosure agreement is required with qualcomm atheros to acce ss this tool. electrical characteristics symbol parameter test conditions min max units vdd supply voltage (error! reference source not found 3.0 3.6 v v il low-level input voltage 0.8 v v ih high-level input voltage 2.0 v v ol low-level output voltage i ol = 4 ma, 12ma (error! reference source not found) 0.4 v v oh high-level output voltage i oh = -4 ma, -12ma (error! reference source not found) 2.4 v i il low-level input current v i = gnd -1 a i ih high-level input current v i = 3.3v 1 a i oz high-impedance output current gnd < v i <3.3v -1 +1 a t op operating temperature range -40 +85 c 1. a typical supply current, assuming a nominal op eration of 50% transmit and 50% receive duty cycle, is 580 ma. 2. iol=12 ma for all gpios. iol = 4 ma for all oth er digital interfaces. 3. ioh = -12 ma for all gpios. ioh = -4 ma for all other digital interfaces.
0804-5000-25 industrial powerline module techhelp@belf.com belpowersolutions.com 11 mechanical 0804-5000-25 horizontal mount

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